Registrations Open for Project based
Industrial Training with Internship - 2024
+91-9876795015
+91-9876795015
Managed By : ICS Group
Pioneering Industry Leading Training & Skill Development Since 1999
Creating a Future - Ready Workforce in India
Pioneering Industry Leading Training & Skill Development Since 1999
Creating a Future - Ready Workforce in India
We offer the following training modules in VLSI - VHDL
CMOS
- MOS Fundamentals and Characterization
- NMOS/PMOS/CMOS Technologies
- Fabrication Principles
- Different Styles of Fabrication for NMOS/PMOS/CMOS
- Design with CMOS Gates
- Characterization of CMOS Circuits
- Layout Representation for CMOS Circuits
- Design Exercise using CMOS
- Scaling Effects
- Sub-Micron Designs
- Parasitic Extraction and Calculations
- Subsystem Design
- Introduction of IC Design
- Different Methodologies for IC Design
- Fabrication Flows and Fundamentals
VHDL
- VHDL Overview and Concepts
- Levels of Abstraction
- Entity, Architecture
- Data Types and declaration
- Enumerated Data Types
- Relational, Logical, Arithmetic Operators
- Signal and Variables, Constants
- Process Statement
- Concurrent Statements
- When-else, With-select
- Sequential Statement
- If-then-else, Case
- Slicing and Concatenation
- Loop Statements
- Delta Delay Concept
- Arrays, Memory Modeling, FSM
- Writing Procedures
- Writing Functions
- Behavioral / RTL Coding
- Operator Overloading
- Structural Coding
- Component declarations and installations
- Generate Statement
- Configuration Block
- Libraries, Standard packages
- Local and Global Declarations
- Package, Package body
- Writing Test Benches
- Assertion based verification
- Files read and write operations
- Code for complex FPGA and ASICs
- Generics and Generic maps
VERILOG
- Language introduction
- Levels of abstraction
- Module, Ports types and declarations
- Different Styles of Fabrication for NMOS/PMOS/CMOS
- Registers and nets, Arrays
- Identifiers, Parameters
- Relational, Arithmetic, Logical, Bit-wise shift Operators
- Writing expressions
- Behavioral Modeling
- Structural Coding
- Continuous Assignments
- Procedural Statements
- Always, Initial Blocks, begin ebd, fork join
- Blocking and Non-blocking statements
- Operation Control Statements
- If, case
- Loops: while, for-loop, for-each, repeat
- Combination and sequential circuit designs
- CMOS gate modeling
- Writing Tasks
- Writing Functions
- Compiler directives
- Conditional Compilation
- System Tasks
- Gate level primitives
- User defined primitives
- Delays, Specify block
- Testbenchs, modeling, timing checks
- Assertion based verification
- Code for synthesis
- Advanced topics
- Writing reusable code
System Verilog
- Introduction to System Verilog
- System Verilog Declaration spaces
- System Verilog Literal Values and Built-in Data Types
- System Verilog User-Defined and Enumerated Types
- System Verilog Arrays, Structures and Unions
- System Verilog Procedural Blocks, Tasks and Function
- System Verilog Procedural Statements
- Modelling Finite State Machines with System Verilog
- System Verilog Design Hierarchy
- System Verilog Interfaces
- Behavioral and Transaction Level Modelling
FPGA Flow
- Re-configurable Devices, FPGA’s/CPLD’s
- Architectures of XILINX, ALTERA Devices
- Designing with FPGAs
- FPGA’s and its Design Flows
- Architecture based coding
- Efficient resource utilization
- Constrains based synthesis
- False paths and multi cycle paths
- UCF file creation
- Timing analysis/Floor Planning
- Place and route/RPM
- Back annotation, Gate level simulation, SDF Format
- DSP on FPGA
- Writing Scripts
- Hands on experience with industry Standard Tools
ASIC Flow
Projects: As a part of course 2 mini projects and 1
major project
- EDA Tools / CAD Flow for IC Design
- Simulation/Synthesis using ASIC libraries
- Clock Tree Synthesis
- False paths / Multi cycle paths / Critical paths
- Design for Testability (DFT)
- Scan Insertion / Types of Scan
- Fault Models
- Logic BIST, Memory BIST, ATGP, Boundary Scan
- Pattern Compression
- Scan Diagnostics
- Layout Design
- Placing and Routing
- LVS/DRC/OPC/Physical verification
- Diagnosis, DFM, Yield Analysis
- SOC Design and Trade-offs
- Future Trends and challenges
- ASIC Case Studies
News and Events
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Chandigarh Office
TCIL-IT (ICS)
S.C.O. 3017-18, Second Floor
Opp. Kisan Bhavan (Bijwara Market)
Sector 22D, Chandigarh- 160 022
Phone:
0172 - 4634529
Mobile:
+91 9876795015
Email:
tcilchd@gmail.com
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